This invention relates generally to packaged integrated circuits in which the substrate of the integrated circuit is unconnected to an external package pin and, more particularly, to a method and apparatus for forcing the substrate to a predetermined voltage during package level testing.
Many types of integrated circuits employ on-chip substrate bias generators (also known as "charge pumps") for enhanced performance by lowering the junction capacitance between diffused areas and the substrate, and by reducing the body effect on integrated field-effect transistors ("FETs"). Charge pumps are typically used on complimentary metal-oxide semiconductor ("CMOS") memory circuits such as static random-access memories ("SRAMs") and dynamic random-access memories ("DRAMs"), but are not limited to these applications.
Referring now to FIG. 1, a simplified block diagram of a packaged integrated memory circuit 10 includes a package 12, external package pins 14, and dedicated package pins 16, 18, 20, and 22. External package pins 14 typically provide electrical connection for address busses and control functions for the memory. Pin 16 provides electrical connection to a first power supply voltage VCC, pin 18 provides electrical connection to a second power supply voltage VSS, pin 20 receives an inverted chip select signal, and pin 22 receives an inverted output enable signal. Pins 14-22 are only shown as being representative of a typical memory circuit but other varied configurations are possible. It is important to note that the substrate is not connected to any of the external package pins.
Inside the package, the integrated circuit includes a primary memory circuit 26, a charge pump 24, and a substrate 28. The charge pump 24 and memory circuit 26 are integrated together in a single integrated circuit, which is in physical and electrical contact with the substrate 28. Conductors 30 and 32 are shown only to illustrate the substrate voltage. The charge pump 24 is powered by VCC and VSS and generates the -1 volt VBB voltage for driving the substrate. In turn, the entire substrate is biased to -1 volts, including the portion underlying the memory circuit 26.
Integrated circuit memory circuits are typically tested at wafer sort where, since the integrated circuit has not yet been packaged, the substrate can be readily electrically contacted. During testing, the positive power supply voltage VCC and the substrate voltage VBB are varied in order to stress certain failure mechanisms and identify both failed and marginally performing circuits. Once the integrated circuits are packaged, however, access to the substrate is lost and the ability to stress failure mechanisms related to the substrate voltage is diminished.
Accordingly, a need remains for a mechanism for forcing the internal substrate voltage VBB once the integrated circuit has been packaged to allow more thorough testing.